1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a four-mask process thin film transistor (TFT) array substrate and method for fabricating the same that prevent a semiconductor tail from being formed. An open area is obtained and wavy noise is prevented from occurring.
2. Discussion of the Related Art
Among the various flat displays, LCD devices have attracted much attention because of their high contrast ratio, good gray scale, high-quality moving picture image, and low power consumption.
Various patterns of driving elements or lines are provided on a substrate to drive an LCD device. These patterns may be formed by photolithography.
Photolithography involves complicated steps such as coating a film layer of a substrate with photoresist which is sensitive to ultraviolet rays, performing exposure and development of the substrate after positioning an exposure mask above the substrate, etching the film layer by using the patterned photoresist as a mask, and stripping the photoresist.
A TFT array substrate of a related art LCD device may include a gate line layer, a gate insulation layer, a semiconductor layer, a data line layer, a passivation layer, and a pixel electrode. Typically, five to seven masks are needed in order to form the above-mentioned elements on the TFT array substrate. Increasing the number of masks used by photolithography results in a greater probability of defects.
Recently, to overcome this problem, low-mask technology has been actively studied, which improves productivity and improves the process margin by fabricating the substrate using the minimum number of masks and photolithography.
Hereinafter, a method for fabricating a related art TFT array substrate will be explained with reference to the accompanying drawings.
FIGS. 1A to 1G are cross sectional views illustrating a method for fabricating a related art TFT array substrate. FIG. 2 is a cross sectional view illustrating defects of a related art TFT array substrate.
To form the related art TFT array substrate of the LCD device, as shown in FIG. 1A, aluminum neodymium (AlNd) and molybdenum (Mo) are deposited on a substrate 11, and are patterned by photolithography using a first mask, thereby forming a multitude of gate lines (not shown), a gate electrode 12a, a lower capacitor electrode 32, and a gate pad electrode (G.P) 22. The multitude of gate lines, the gate electrode 12a, and the lower capacitor electrode 32 are formed in an active region, and the gate pad electrode (G.P) 22 is formed in a pad region.
Then, an inorganic material of silicon oxide (SiOx) or silicon nitride (SiNx), by way of example, is deposited on an entire surface of the substrate 11 including the gate electrode 12a under high temperature conditions, thereby forming a gate insulation layer 13. Thereafter, an amorphous silicon layer (a-Si) 14d and a metal layer 15d of molybdenum (Mo) are sequentially deposited on the entire surface of the substrate 11 including the gate insulation layer 13. Thereon, a photoresist 50 is coated and is patterned by photolithography using a second mask, thereby patterning the photoresist 50 having a step coverage. The second mask may be a diffraction exposure mask, for example, a slit mask or a half-tone mask, to form the step coverage in the photoresist.
Then, the exposed amorphous silicon layer 14d and metal layer 15d are etched using the photoresist 50 having the step coverage as a mask, thereby forming a multitude of data lines (not shown), source and drain electrodes 15a and 15b, and a semiconductor layer 14, as shown in FIG. 1B. A two-step etching method is applied that includes a wet-etching step for the metal layer 15d and a dry-etching step for the amorphous silicon layer 14d. 
As shown in FIG. 1C, the thickness of the photoresist 50 is decreased by ashing the photoresist 50, to thereby expose the metal layer corresponding to a channel region of a thin film transistor (TFT). Then, the exposed metal layer is etched by wet-etching so that the source and drain electrodes 15a and 15b are separated from each other, thereby further defining the channel region.
When ashing the photoresist, the width and thickness of photoresist are decreased, whereby an active layer 14 and the source/drain electrodes 15a/15b slightly protrude out of the edge of the photoresist. When performing wet-etching to separate the source and drain electrodes from each other, the protruding portion of the metal layer is etched together, but the active layer is not etched. The protruding portion of the active layer, which is protruding out of the source and drain electrodes, is referred to as a semiconductor tail 14a. 
As shown in FIG. 2, the semiconductor tail 14a protrudes out from the data line 15 as well as the source and drain electrodes 15a and 15b. 
Accordingly, an active region includes a plurality of data lines (not shown), a semiconductor layer 14, source/drain electrodes 15a/15b, and a pad region with a data pad electrode (not shown). The semiconductor layer may be etched with the data line and the source/drain electrodes together, so that the semiconductor layer has substantially the same pattern as that of the data line and the source/drain electrodes.
Thus, the deposited gate electrode 12a, gate insulation layer 13, semiconductor layer 14 and source/drain electrodes 15a/15b form the thin film transistor that controls the voltage-on/off state applied to a sub-pixel.
As shown in FIG. 1E, after removing the photoresist 50, an organic insulation material of BCB or an inorganic insulation material of SiNx is formed on the entire surface of the substrate including the source and drain electrodes 15a and 15b, thereby forming a passivation layer 16.
After that, as shown in FIG. 1F, the passivation layer 16 is partially removed by photolithography using a third mask, to thereby form a contact hole 71 which exposes the drain electrode 15b. By removing the passivation layer 16 and the gate insulation layer 13, a pad open area 81 is formed to expose the gate pad electrode 22. Although not shown, a pad open area is also formed to expose the data pad electrode.
As shown in FIG. 1G, a transparent conductive material of Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), by way of example, is deposited on the entire surface of the substrate including the passivation layer 16, and is then patterned by photolithography using a fourth mask, to thereby form a pixel electrode 17 connected with the drain electrode 15b. Thus, the TFT array substrate is completed. At the same time, a transparent conductive layer 27 is formed to cover the pad open area, thereby preventing the gate and data pad electrodes from being oxidized.
Four exposure masks are required to form the TFT array substrate.
However, the related art TFT array substrate and the method for fabricating the same have the following disadvantages.
Forming the pattern of the TFT array substrate by the four diffraction exposure masks necessarily requires the process of patterning the data line layer and the semiconductor layer. A semiconductor tail is formed at the edge of the source/drain electrodes and data line, when defining the channel region by separating the source and drain electrodes from each other after ashing the photoresist having the step coverage. As shown in FIG. 2, the semiconductor tail 14a having a width of about 1.5 μm is formed at the edge of the data line 15, which causes the device to malfunction.
The semiconductor tail causes ‘wavy noise’ when turning on/off a backlight unit (B/L). The conductive properties of the semiconductor layer are changed based on the application of light. That is, if light is applied to the semiconductor layer, the semiconductor layer becomes conductive. If light is not applied to the semiconductor layer, the semiconductor layer becomes nonconductive.
If the backlight unit is turned off, a parasitic capacitance occurs between the data line 15 and the pixel electrode 17 owing to the semiconductor layer having no conductivity. Meanwhile, if the backlight unit is turned on, the semiconductor layer, which is more adjacent to the pixel electrode than the data line, becomes conductive whereby the parasitic capacitance occurs between the semiconductor layer 14 and the pixel electrode 17.
Because of the width of the semiconductor tail 14a, the data line 15 differs in size from the semiconductor layer 14. Thus, the parasitic capacitance generated between the data line 15 and the pixel electrode 17 is different from the parasitic capacitance generated between the semiconductor layer 14 and the pixel electrode 17. That is, the parasitic capacitance increases between the semiconductor layer and the pixel electrode because the semiconductor layer is substantially larger than the data line. Because parasitic capacitance changes as a function of the voltage-on/off state of the backlight unit, a wavy noise occurs on images.
Also, the pixel electrode 17 is at a predetermined distance from the data line 15 and the semiconductor layer 14 (about 5.0 and 3.5 μm, respectively). Thus, the pixel electrode 17 is further from the data line 15 by the width (about 1.5 μm) of the semiconductor tail 14a, whereby an open area decreases. Also, the area of a black matrix 90 is increased according to the semiconductor tail, wherein the black matrix 90 prevents light from leaking, so that the aperture ratio of the device is decreased.
Also, the turn-off current of the device increases due to the photocurrent generated by the semiconductor tail.